The SLF performs logical and arithmetic operations and generates specific data and logic outputs. The SLF accepts an instruction command of 4 bits. This command specifies details of the operation. The fundamental logical operation of the SLF is the limit function. The SLF consists of three registers, Upper (U), Parameter (P), and Lower (L). One of these registers is picked as the output, Q, at the end of the word. Register L is picked if P < L (algebraically), register U is picked if P >U and not <L (algebraically), otherwise register P is picked if U >= P >=L (algebraically). Other logical functions, such as, logical products, Gray code conversions, forced 1's, forced 0's, and two's complements operations are performed. The 20-bit logical operations are accomplished in one word time of 106.6 microseconds.
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